1. Field of the Invention
The present invention relates to semiconductor devices and, more particularly, insulated gate bipolar transistors (IGBT: Insulated Gate Bipolar Transistor).
2. Description of the Background Art
Power ICs formed by integrating power elements having high breakdown voltage and large current characteristics together with a drive circuit and a protection circuit thereof are expected to be the mainstream of future power elements. A preferable gate driving method for such a power element is a voltage-controlled type using an insulated gate electrode (MOS gate) because the voltage-controlled type enables gate drive with less current than that required for a current-driven type.
Among integrated circuits (IC) manufactured by integrating a plurality of semiconductor devices on a single semiconductor substrate, an IC containing a high breakdown voltage element is called a power IC. A transistor including a MOS gate which is commonly used as such a high breakdown voltage element (power MOSFET, IGBT, etc.) has its channel portion ordinarily formed by the DSA (Diffusion Self Alignment) method. In the DSA method, a source diffusion layer and a channel diffusion layer having the opposite polarity to that of the source diffusion layer are formed by using one end surface of the same polysilicon gate electrode as a diffusion window.
FIG. 19 is a sectional view showing a horizontal IGBT manufactured by the conventional DSA method. With reference to FIG. 19, in the conventional IGBT, a p-type base layer 3 is formed in a predetermined region of the main surface of a high-resistance n-type substrate 1 constituting an n-type base layer. An n-type emitter layer 5 is formed in a predetermined region of the main surface of p-type base layer 3. A gate electrode 2 is formed on a region between n-type emitter layer 5 and n-type base layer 1 and on a predetermined region of the main surface of n-type base layer 1, with a gate insulating film 2a interposed therebetween. A p-type collector layer 4 is formed in a region of the main surface of n-type base layer 1 located at a predetermined interval from the above n-type base layer 3. An emitter electrode 18, a gate contact electrode 19 and a collector electrode 20 are respectively formed on n-type emitter layer 5, gate electrode 2 and p-type collector layer 4 to be in contact therewith.
In the process for manufacturing p-type base layer 3, n-type emitter layer 5 and p-type collector layer 4 of the horizontal IGBT shown in FIG. 19, an impurity is first diffused into n-type base layer 1 from the left of the position A in the figure by using gate electrode 2 as a mask to form p-type base layer 3. Then, p-type collector layer 4 is formed by diffusing an impurity into a region of the main surface of n-type base layer 1 located at a predetermined distance from p-type base layer 3. In the same manner as in the formation of p-type diffusion layer 3, an n-type impurity is diffused from the left of the position A by using gate electrode 2 as a mask to form n-type emitter layer 5.
In the conventional horizontal IGBT shown in FIG. 19, application of a positive voltage with respect to a potential of n-type emitter layer 5 to gate electrode 2 results in formation of an n-type channel in the main surface of p-type base layer 3 located under gate electrode 2. As a result, electrons flow into p-type collector layer 4 through n-type base layer 1. At this time, holes are introduced into n-type base layer 1 from p-type collector layer 4 so as to satisfy charge neutrality conditions. Conductivity modulation then occurs to result in a lower ON-state voltage than that of a power MOSFET. Since a switching loss is a product of an ON-state voltage and a turn-off time, the ON-state voltage should be low and the turn-off time should be short in order to reduce power consumption. While the conventional IGBT allows its ON-state voltage to be lower than that of a power MOSFET, it does not allow further reduction of its ON-state voltage with ease.
In addition, a conventional power IC requires an IGBT, a high breakdown voltage element, and a low breakdown voltage element for constituting a logic circuit such as a CMOS to be formed on the same semiconductor substrate. FIG. 20 is a sectional view of a conventional n-channel MOSFET. With reference to FIG. 20, in the MOSFET, a p-type well diffusion layer 6 is formed in a predetermined region of the main surface of an n-type semiconductor substrate 1. N-type diffusion layers 8 and 9 constituting source/drain regions are formed at a predetermined interval from each other in predetermined regions of the main surface of p-type well diffusion layer 6 so as to sandwich a channel region. A gate electrode 7 is formed on the channel region with a gate insulating film 7a interposed therebetween. A source electrode 101, a gate contact electrode 102 and a drain electrode 103 are formed on n-type diffusion layer 8, gate electrode 7 and n-type diffusion layer 9, respectively.
Description will be given of a conventional process of manufacturing an n-channel MOSFET in a case where the n-channel MOSFET, a low breakdown voltage element shown in FIG. 20, and the IGBT, a high breakdown voltage element shown in FIG. 19, are formed on the same substrate. First, a p-type well diffusion layer 6 is formed in a predetermined region of the main surface of n-type semiconductor substrate 1 having the same resistance as that of a high breakdown voltage element. Then, gate electrode 7 is formed on a predetermined region of the main surface of p-type well diffusion layer 6 with gate insulating film 7a interposed therebetween. Thereafter, n-type diffusion layers 8 and 9 constituting source/drain regions are formed by implanting ions of an n-type impurity into p-type well diffusion layer 6 using gate electrode 7 as a mask. Then, source electrode 101, gate contact electrode 102 and drain electrode 103 are formed on n-type diffusion layer 8, gate electrode 7 and n-type diffusion layer 9, respectively. Thus, such a low breakdown voltage n-channel MOSFET as shown in FIG. 20 is obtained.
When in forming the structures shown in FIGS. 19 and 20 on the same substrate, both of p-type base layer 3 of the high breakdown voltage element (IGBT) shown in FIG. 19 and p-type well diffusion layer 6 of the low breakdown voltage element (MOSFET) shown in FIG. 20 are diffusion layers for forming channel portions. However, while the p-type channel portion of the high breakdown voltage element uses a horizontal diffusion region of p-type base layer 3, the p-type channel portion of the low breakdown voltage element uses a longitudinal diffusion region of p-type well diffusion layer 6. For forming the channel regions of the low breakdown voltage element and the high breakdown voltage element to have the same impurity concentration, it is therefore necessary to make the amount of impurity diffusion at the time of forming p-type base layer 3 different from that at the time of forming p-type well diffusion layer 6. This conventionally makes it difficult to form p-type base layer 3 and p-type well diffusion layer 6 by the same process.